Several processes and techniques for transferring semiconductor layers, such as Si or SiGe layers, have been proposed, in which the donor wafer comprises in succession a single-crystal silicon support substrate and a thickness of SiGe. Zhi-Yuan Cheng et al. of Massachusetts Institute of Technology has presented, in a document entitled “SiGe-On-Insulator (SGOI): Substrate Preparation and MOSFET Fabrication for Electron Mobility Evaluation” (2001 IEEE International SOI Conference, 10/01), two known techniques for transferring layers applied to the donor wafer including a SiGe buffer layer.
The first of these layer transfer techniques is called “etch-back”. It consists of removing, by chemical-mechanical means, the single-crystal Si support substrate and the SiGe buffer layer after bonding the donor wafer to the receiving substrate. In particular, an etching called “selective etching” is used to remove the buffer layer, as this has the ability of etching the strained SiGe of the buffer layer more easily than the relaxed SiGe of the surface layer. The relaxed SiGe layer then behaves as a “stop layer” for the etching, since the etching stops at least partly at the level thereof.
Finally, a strained Si film is then grown epitaxially on the relaxed SiGe layer in order to produce a strained Si-on-SiGe structure. In this final structure, a layer of relaxed material (in this case, the layer of SiGe) is interposed between the layer of strained material (in this case the Si film) and the oxide.
This may substantially reduce the technical performance expected of the Si/SiGe combination, and especially its electrical properties. Thus, for example, the SiGe layer may have a tendency to increase the circuit capacitances and therefore reduce the switching rates of the electronic components to be produced or produced in the Si/SiGe active part.
The fabrication of electronic components in the active part of such a structure comprising this combination having two on-insulator layers also has the risk of being complex to carry out, especially by the creation of lateral insulating regions in the on-insulator combination. This process furthermore limits the application to the production of an Si/SiGe-on-insulator structure and provides no solution to the production, for example, of a strained Si-on-insulator structure.
Other etch-back techniques and processes have also been proposed, for example, in U.S. Pat. No. 5,013,681, in which an unstrained Si layer is especially transferred;
The second layer transfer technique reported in the document by Zhi-Yuan Cheng et al. is based on the “SmartCut®” technology of Soitec S.A., which is known to those skilled in the art, and descriptions of which may be found in a number of works dealing with wafer reduction techniques. In the SmartCut® process, before bonding, an ion species is implanted into the relaxed SiGe layer to create a region of weakness therein. After bonding, the donor wafer splits or is cut at the region of weakness. What is obtained therefore is, on the one hand, a donor wafer, stripped of part of the relaxed SiGe layer, and, on the other hand, a structure comprising, bonded together, a removed thin layer of relaxed SiGe and the receiving substrate. The SmartCut® technique is advantageous in that it affords the possibility of recycling the donor wafer instead of sacrificing it, unlike the etch-back technique.
Other processes have been proposed, using the two techniques simultaneously. U.S. Pat. No. 5,882,987 and a document by K. D. Hobart et al. from the Naval Research Laboratory in Washington (“On scaling the thin film Si thickness of SOI substrates”) disclose an overall process for producing a “semiconductor-on-insulator” (also called SeOI) structures from a donor wafer comprising in succession a single-crystal Si base support substrate, an SiGe layer and an epitaxially grown Si film bonded to an oxidized support substrate. In these disclosures, the SmartCut® technique is employed, creating, before bonding, a region of weakness in the Si support substrate which, after bonding, causes detachment in the donor wafer in this region. A structure consisting in succession of part of the Si support substrate, the SiGe layer and the epitaxially grown Si film is thus removed, the whole assembly being bonded to the oxidized receiving substrate.
Two successive selective etching operations are then carried out on the structure firstly to remove the remaining part of the Si support substrate with an etching solution, such that the SiGe layer forms a stop layer, and then to remove the SiGe layer with an etching solution such that the Si film forms a stop layer. The resulting structure is an SeOI structure with a surface Si layer. This silicon layer is both very thin and very uniform through its thickness, and is provided using a process which can avoid a finishing step which would otherwise be prejudicial to the quality of the silicon layer. The main objective of this process is not, however, to produce an SeOI structure with a strained silicon layer. The SiGe layer used to produce the SeOI structure during implementation of this process has a typical thickness of between 0.01 and 0.2 microns, a thickness insufficient to fulfill the role of a buffer layer between the Si support substrate and a potential relaxed SiGe layer. The silicon of the film grown epitaxially on the SiGe layer and constituting the Si layer of the final SeOI structure therefore would be little strained or unstrained, and therefore does not achieve production of a structure comprising a strained Si layer so as to benefit from its useful electrical properties, especially in SeOI structures. Also, since the instruments for implanting species are very often limited to about 200 keV, the associated maximum implantation depths would correspond substantially to the minimum thickness of a reliable buffer layer, i.e., about one to two microns, which is insufficient to implant into the Si support substrate, so it would be difficult to use this process with an SiGe layer thick enough to contain both a buffer layer and a relaxed surface SiGe layer. More powerful implantation instruments require an equipment infrastructure that would be very expensive and the operating costs could be prohibitive. This type of process therefore seems to be unsuitable for producing a structure comprising a strained Si layer.
An IBM document by L. J. Huang et al. (“SiGe-On-Insulator prepared by wafer bonding and layer transfer for high-performance field-effect transistors”, Applied Physics Letters, 26, Feb. 2001, Vol. 78, No. 9), discloses for example a process for producing an Si/SGOI structure with strained silicon, starting from a donor wafer comprising in succession a single-crystal Si support substrate, a SiGe buffer layer and a relaxed SiGe layer. The process employed consists in using the SmartCut® technique in the relaxed SiGe layer, thus making it possible, after bonding to an oxidized receiving substrate and after cutting in the region of weakness created beforehand, to produce a SGOI structure with relaxed SiGe. A film of strained Si is then epitaxially grown on the relaxed SiGe layer in order to produce a Si/SGOI structure. In this final structure, a layer of relaxed material (i.e., the SiGe layer) is subjacent to the layer of strained material (i.e., the Si film). This may be prejudicial to the performance, especially the electronic performance, expected in this case of the layer of strained material, as already mentioned above. This process furthermore limits the application to the production of such a Si/SiGe-on-insulator structure and does not provide a solution to the production, for example, of a strained Si-on-insulator structure.
PCT Publication WO 01/99169 discloses processes for producing, from a wafer consisting in succession of a Si substrate, a SiGe buffer layer, a relaxed SiGe layer and, optionally, a layer of strained Si or SiGe, a final structure having the relaxed SiGe layer on the optional other strained Si or SiGe layer. The technique employed to produce such a structure involves, after bonding the wafer to a receiving substrate, removal of material from the wafer that it is not desired to retain, by selectively etching the Si substrate and the SiGe buffer layer. This technique does make it possible to achieve thin layer thicknesses having homogeneity through the thickness, but it does entail, however, the destruction of the Si substrate and of the SiGe buffer layer by chemical etching. These processes do not therefore afford the possibility of reusing part of the wafer, and especially at least part of the buffer layer, for a new layer transfer. Moreover, these processes do not provide a solution to the production of a simple strained silicon-on-insulator structure.
Accordingly, there is a need for a process to produce strained silicon-on-insulator which can overcome the above drawbacks.